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Graphics Interchange Format  |  1999-09-30  |  39.8 KB  |  653x372  |  4-bit (16 colors)
   ocr: Figure 3. The Rational Unified Process (RUP)1 Life Cycle <<trace>? <<trace>> <<trace>> Requirements Design Implementation Test Hodel Model <<trace>> Model *s<Uace>> l Model 4 <<race>> - iter. #1 iter.1 iter #1 iter.# <<trace>> <strace>> <<trace>> <<trace>> s<trace>> <<trace>> <<trace>> Requirements Design Implementation Test Model Model + - s<trace> Nodel + <<trace>> Modal *<<trace>> à - iter.#2 iter. #2 iter. E2 iter. #2 <<trace>> <<trace>> <<trace>> <trace> - a - <<traces <<trace>> <<trace>> iter. Model Requirements #3 <ctrate>>- iter. Desizn Model #3 * <<trace>>* iter. Model mplementation # ...